1. Field of the Invention
The invention in general relates to the structure and fabrication of integrated circuits and more particularly to a process for fabrication of a stacked capacitor DRAM.
2. Statement of the Problem
As is well-known, integrated circuits, sometimes called semiconductor devices, are generally mass produced by fabricating hundreds of identical circuit patterns on a single semiconducting wafer, which wafer is subsequently sawed into hundreds of identical dies or chips. While integrated circuits are commonly referred to as "semiconductor devices" they are in fact fabricated from various materials which are either electrically conductive, electrically nonconductive, or electrically semiconductive. Silicon, the most commonly used semiconductor material, can be used in either the single crystal or polycrystalline form. In the integrated circuit fabrication art, o polycrystalline silicon is usually called "polysilicon" or simply "poly", and shall be referred to as such herein. Both forms of silicon may be made conductive by adding impurities to it, which is commonly referred to as "doping". If the doping is with an element such as boron which has one less valence electron than silicon, electron "holes" become the dominant charge carrier and the doped silicon is referred to as P-type silicon. If the doping is with an element such as phosphorus which has one more valence electron than silicon, additional electrons become the dominant charge carriers and the doped silicon is referred to as N-type silicon.
CMOS (Complimentary Metal Oxide Semiconductor) technology is currently the most commonly used integrated circuit technology, and thus the present invention will be described in terms of silicon-based CMOS technology, although it is evident that it may find uses in other integrated circuit technologies. The term CMOS is now loosely applied to mean any integrated circuit in which both N-channel and P-channel MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) are used in a complimentary fashion. It should be noted here that because the dominant carrier in a MOSFET occurs in an inversion layer, the channel of an N-channel MOSFET is actually doped P-type and the channel of a P-channel MOSFET is actually doped N-type. CMOS integrated circuit o fabrication may begin with a lightly-doped P-type silicon substrate, a lightly-doped N-type silicon substrate, or lightly-doped epitaxial silicon (deposited crystalline silicon) on a heavily doped substrate. For the sake of simplicity, the invention will be described using lightly-doped P-type silicon as the starting material, although it may be implemented with other materials as the starting point. If other materials are used as the starting point, there may be differences in materials and structure as is well-known in the art, e.g. with N-type silicon as the starting point dopant types may be reversed, or P-type wells may be introduced.
One well-know integrated fabrication process is the photo-mask and etch process which comprises: creating a photolithographic mask containing the pattern of the parts to be fabricated, coating the integrated circuit wafer with a light-sensitive material called photoresist or resist, exposing the resist-coated wafer to ultraviolet light through the mask to soften or harden parts of the resist depending on whether positive or negative resist is used, removing the softened parts of the resist, etching the wafer to remove the part unprotected by the resist, and stripping the remaining resist. Etching which forms part of the photo-mask and etch process is itself a highly developed process which is used in many instances besides in conjunction with the photo-mask. It is well-know that etches can be made that etch one material relatively rapidly while etching another material hardly at all. When an etch does not etch a material it is said to be "selective" to that material. That is, it selectively leaves that material while etching away other materials.
Most current-generation DRAM (Dynamic Random Access Memory) manufactures utilize CMOS technology. DRAM circuits comprise arrays of memory cells, each cell comprising two main components: a field effect transistor and a capacitor. In the most common circuit designs, one side of the transistor is connected to one side of the capacitor, the other side of the transistor and the transistor gate are connected to external connection lines called the bit line and word line, respectively, and the other side of the capacitor is connected to a reference voltage that is typically 1/2 the internal circuit voltage. Thus the fabrication of the Dram cell essentially comprises the fabrication of a transistor, a capacitor, and three contacts to external circuits.
The advantages of building integrated circuits with smaller individual circuit elements so that more and more circuitry may be packed on a single chip are well-known: electronic equipment becomes less bulky, reliability is improved by reducing the number of solder or plug connections, assembly and packaging costs are minimized, and improved circuit performance, in particular higher clock speeds. The requirements of holding a charge large enough to be sensed for a long enough time for practical memory applications result in the capacitor being the largest of the circuit parts. Thus, the drive to produce smaller DRAM circuits has give risen to much capacitor development, which can be classified into three basic capacitor types: planar capacitors, trench capacitors and stacked capacitors. For reasons of available capacitance, reliability, and ease of fabrication, most manufacturers of DRAMS of 4-Megabit and larger capacity utilize stacked capacitor designs in which the capacitor covers nearly the entire area of a cell and in which vertical portions of the capacitor contribute significantly to the total charge storing capacity. In such designs the side of the capacitor connected to the transistor is generally called the "storage node" or "storage poly" since the material out of which it is formed is doped polysilicon, while the polysilicon layer defining the side of the capacitor connected to the reference voltage mentioned above is called the "cell poly".
An area in a integrated circuit to which electrical connection is to be made is generally called an active area (A.A.). As capacitors have covered ever larger areas of individual cells and as the size of the cells has shrunk, the size of active areas as well as the corridors available for contacts to reach the A.A.'s has also shrunk. With these smaller spaces, the chances for leakage between the contacts and transistor and capacitor components and the chances of high resistance or open circuit contacts has increased. Thus a DRAM structure and fabrication process that provides more effective isolation of the contacts from the other parts of the DRAM circuit, optimizes the area in which contact may be made, and at the same time permits smaller contacts is highly desirable.
The business of fabricating CMOS semiconductor devices is a very competitive, high-volume business. Thus manufacturing efficiency is highly important. Product quality and reliability are also highly important. It is well-known in the art that reducing the number of mask steps in the integrated circuit manufacturing process not only reduces manufacturing costs and time but also generally increases the quality and reliability of the end product, since the opportunities for disabling defects to occur are reduced. This in turn feeds back into further reduced manufacturing costs since scrapped product is reduced. Thus, a circuit structure and process that not only permits more compact devices but also reduces the number of fabrication steps, particularly the number of mask steps, would be a significant advance in the art.
One approach to solving the above problems in a state-of-the-art DRAM fabrication process is described in "A 1.28 .mu.m.sup.2 Bit-line Shielded Memory Cell Technology for 64 Mb DRAMs", by Y. Kawamoto et al, in IEEE 1990 Symposium on VLSI Technology, pp. 13-14. This fabrication uses a single photo step to define the storage node contacts and storage poly. This results in a reduced number of mask steps. However, this method also results in a buried bit-line which requires that the bit line be subjected to the subsequent steps in forming the capacitor which generally includes high temperature. Thus the bit line must be formed out of a temperature-resistant material, such as a silicide, which has higher resistance than a metal such as aluminum or tungsten and thus reduces the speed of the DRAM. In addition, the use of a silicide bit line requires two additional photo steps. i.e. the A.A. to silicide bit line contact photo and the silicide bit line photo.
Another approach is disclosed in "Two step Deposited Rugged Surface (TDRS) Storagenode and Self-Aligned Bitline-Contact Penetrating Cellplate (SABPEC) for 64 Mb DRAM STC Cell" by H. Itoh et al. in IEEE 1991 Symposium on VLSI Technology, pp. 9-10. See also "A Novel Zero-overlap/Enclosure Metal Interconnection Technology For High Density Logic VLSI's", by H. Shibata al. in IEEE Jun. 12-13 1990 VMIC Conference, pp. 15-21. The process and structure disclosed in the H. Itoh reference solves some of the above problems by utilizing a bit line contact that passes through the cell poly, since this technology allows the bit line is formed after the capacitor. However, to insulate the bit line from the cell poly, two layers of insulation must be formed between the word lines, i.e. the word line spacers and the cell poly spacers. This greatly narrows the well for the bit line, and as a result the process is forced to use a poly/silicide bit line since metal would not properly fill such a narrow well. This again requires two additional photo steps. Moreover, in 64 Mbit DRAM technology the gap between the word line spacers is only about 0.2 .mu.m prior to the bit line contact definition. Thus the well between the spacers would be completely closed off with any cell poly oxide spacer thickness greater than 0.1 .mu.m. A spacer this thin is very difficult to form, and would likely result in an unacceptably large number of devices with cell-poly-to-bit-line current leakage. The H. Shibata reference shows a contact plug that penetrates several fabrication layers to contact active areas. The reference discloses polysilicon spacers that do not close off the gaps between transistor gates on either side of the active areas, but would not apply to bit line contacts in DRAM technology as the poly spacers would short the bit line to the cell poly. Further, the approach by Shibata does not self-align the contact with respect to the transistor poly (word lines) and would require the word lines to be spread further apart at the bit contact to allow for misalignment.
A further approach is disclosed in U.S. Pat. No. 5,045,899 issued to Arimoto. This shows a DRAM fabrication process (see FIG. 12 in Arimoto) in which all the oxide is removed prior to deposition of the cell poly. This process does not utilize a self-aligned penetrating bit line contact. Thus it will result in a larger cell size for a given photolithographic capability. Thus a need exists for a DRAM structure and fabrication process which utilizes a self-aligned penetrating bit contact and a reduced number of photo-mask steps, and which is scalable and can utilize metal bit line contacts because it does not close off the gap between the word line spacers in 64 Mbit DRAMs.
3. Solution to the Problem
The present invention provides a method of integrated circuit fabrication that utilizes a single etch stop layer to form three different self-aligned contacts. In DRAM, the single etch stop layer is used to form metal to A.A. contacts that are self aligned to the transistor poly, to form storage poly contacts that are self aligned to the word line poly, and also to form metal 1 to transistor poly contacts without any additional steps.
In providing the above structure and process, the invention provides an integrated circuit that utilizes contact-through-cell-poly technology while also providing a method of making metal-to-cell-poly contacts with no additional photo/etch steps.
The invention further provides an efficient integrated circuit structure and process that, when the overall process is considered, requires fewer mask steps; in particular it provides a structure and o process for making compact multi-megabit DRAM with minimal masking steps which exploit self alignment of multiple elements and provides large cell capacitance for a given cell area.
The present invention is particularly applicable to DRAM in that it provides a process for efficiently forming multiple contacts in combination with a capacitor of large area. However, once its use in DRAM is understood, it is evident that it can be applied in other circuits also.